Annex G (informative) — Expanders and inter-module links

The connections modules make with each other behind the panel: expander headers, digital links such as I2C, and analog links. EIS places one requirement on them, BUS-011 in 6.4: a header that is not the power header either does not mate a Eurorack power ribbon socket, or survives one fitted to it either way round. The rest of this annex is recommended practice.

EIS · An expander header beside the power header power header, 2 × 5 expander, 2 × 5, same key a ribbon fits: survive it expander, 2 × 4 a ribbon does not fit expander, 2 × 6, unshrouded a ribbon fits: survive it A header that is not the power header either does not mate a power ribbon socket or survives one fitted to it, either way round (BUS-011). A different pitch or connector family, or a shrouded header too small for the socket, meets the first; protection on every pin meets the second.

G.1 Expanders

An expander is a second module that adds jacks, controls, or memory to a main module through a short cable behind the panel. The signals on that cable are the maker's own, so EIS does not classify them.

Topic Practice
Port list The expander header as a port, unclassified, named for what it connects to, for example EXPANDER (to main module)
Connector A pin count or connector family that a power ribbon does not fit, or a shrouded header keyed against one; the board labels what the header is
Cable Supplied with the expander, keyed, and long enough for the positions it is meant for, typically 100 mm to 150 mm
Power From the expander's own power header or through the main module, as the manual states; its currents published either way (PWR-001)
Placement The manual states where the expander may sit: next to the main module, in the same row, or in any row the cable reaches

Several module families share an I2C bus between modules, usually on a 3-pin header carrying SDA, SCL, and 0 V. I2C is defined by its own specification, NXP UM10204. So that modules from different makers can share one bus, EIS recommends:

Topic Practice
Logic level 3.3 V logic, with inputs that tolerate 5 V
Pull-ups Fitted only by the products that say so; the manual states their value and whether they can be switched off
Bus loading Total bus capacitance within the I2C limit of 400 pF; a bus across more than one row, or over more than about 1 m of cable, is a design to check, not a default
Addresses and roles The manual lists each address the module answers and whether it acts as controller or target
Header Pin order SDA, SCL, 0 V is common but not universal; the board marks each pin

A link header goes on the port list like an expander header, unclassified, named for its function, for example I2C.

A cable that carries analog signals between modules behind the panel, such as a normalled bus or a chained clock, joins the 0 V of the modules it links (6.3). EIS recommends listing it on the port list with the class its signals would have on a patch jack, so that its levels are known.