Part 3 — Optional interfaces

Interfaces a product may have beyond Core. None is claimed: a product that has one lists it in its claim file and meets its rules, and a product without it owes none of them (4.1). They are LZX's extensions to Eurorack practice, kept apart so that Core stays what every Eurorack product shares.

• 8.1 12 V DC power (PWR-DC12): a second power interface beside the bus, a 12 V DC rail taken at a barrel or multi-pin DC entry, for modules that need more current than a power header carries or run without a bus.
• 8.2 Video on 75 Ω coaxial jacks (VID-75): the 75 Ω coaxial video sync behind the panel, COAX-IN, COAX-OUT, and COAX-THRU, and the tree that carries one video sync to every module of a system.
• 8.3 Video timing: the formats a video sync port lists, each matched to its publication.

A module, a bus board, or an enclosure may have any of them; a power supply may have PWR-DC12; a cable mates PWR-DC12 or VID-75. One rule of video sync is Core: a product that generates or locks to an external video sync takes or gives it at a video sync port on its rear (SIG-018, 7.1).

Contents

• 8.1 12 V DC power (PWR-DC12): PWR-DC12: a barrel or multi-pin DC entry and the DC rail it feeds
• 8.2 Video on 75 Ω coaxial jacks (VID-75): The 75 Ω coaxial interface: the video sync ports COAX-IN, COAX-OUT, COAX-THRU, the video sync tree, and the coaxial cable
• 8.3 Video timing: The formats a video sync port lists

8.1 12 V DC power (PWR-DC12)

PWR-DC12 is the power interface of nominal 12 V DC. Its rules apply to the products that have an entry or an outlet of it, and to the cables between them:

• a module with a rear DC entry;
• a DC entry panel or a bus board with PWR-DC12 outlets that feeds several modules from one entry;
• an enclosure with a case DC entry;
• a power supply that takes 12 V DC and delivers the bus.

The 12 V DC comes from an external adapter, outside EIS, or from a power supply with PWR-DC12 outlets (SUP-009). It enters at a DC entry and feeds a DC rail, one +V and −V pair that each product filters or regulates locally (Terms). The DC rail is separate from the bus (6.4); the rules common to both power interfaces are in 6.1 to 6.3.

A product's filtering, the connectors of its outputs that are not PWR-DC12 outlets, ripple at PWR-DC12 outlets beyond what a power supply publishes (SUP-001), and the adapter it ships with are product documentation, not EIS. The rules for the person fitting a DC entry are in 9.3. The tables are in data/dc_12.json.

DC entries

A product shall publish its DC entry variant: DC-BAR21, DC-BAR25, DC-VH2, DC-DIN4, DC-MF6, or DC-MF8 (DC-001), and the minimum and maximum DC input voltage its DC entry accepts (DC-002). It publishes the current it takes at its DC entry, and the current it delivers at each PWR-DC12 outlet, at 12 V (PWR-001, PWR-002).

The variants are of two kinds:

• A module DC entry, DC-BAR21 or DC-VH2, takes the rail for one module, usually from a PWR-DC12 outlet.
• A case DC entry is defined by its role, not its connector: it is a DC entry that takes an external adapter's output for a row: any DC entry of an enclosure, a power supply, or a bus board, or of a module with PWR-DC12 outlets or row wiring outputs. DC-BAR25, DC-DIN4, DC-MF6, and DC-MF8 are case entries only; DC-BAR21 serves both, a small case on a 2.1 mm adapter among them. It sits on an enclosure, which then has a PWR-DC12 entry, on a power supply, or on a DC entry panel: a module with a PWR-DC12 entry that feeds the supply, the bus board, or its own PWR-DC12 outlets, and then also keeps the outlet rules. The wires from a case DC entry to what it feeds are row wiring (6.1).

A product with a case DC entry shall publish whether its 0 V is bonded to the chassis at the entry, and where (DC-014): in a system fed from an adapter the case DC entry is where the one chassis tie belongs (6.3). EIS recommends that it make the bond, in PWR-008's form, and carry an M4 CHASSIS terminal for straps to the case's other panels.

A DC entry and each PWR-DC12 outlet shall be marked beside it with its polarity, a barrel by its polarity symbol and a multi-pin entry by its +V and −V pins, its nominal voltage, and its maximum current, and a DC entry also with the minimum and maximum input voltage it accepts (DC-011). The trade marks every DC inlet this way, so an adapter or a cable is chosen at the port.

A DC entry shall not use the pinout of a Eurorack 10-pin or 16-pin power header (DC-003). A barrel DC entry, DC-BAR21 or DC-BAR25, shall be center positive (DC-004).

DC-VH2 is a 2-pin JST VH wire-to-board header, rated 10 A with 16 AWG wire and its terminals, that takes power from a PWR-DC12 outlet. Above 5 A, EIS recommends DC-VH2, DC-DIN4, DC-MF6, or DC-MF8 rather than a barrel: a through-hole jack for a 2.1 mm plug is rated 2.5 A to 8 A by its maker (Same Sky PJ-002A 2.5 A and PJ-002AH 5 A, both with a 2.0 mm pin that a 2.1 mm plug takes; PJ-063AH 8 A) and a 2.5 mm jack 5 A to 7 A with a standard plug, and the product publishes its own figure (PWR-001).

EIS recommends that a DC entry accept at least 10.8 V to 13.2 V, ±10 % of 12 V. A 12 V adapter regulates to about ±5 %, and a reverse-polarity diode, the protection of an outlet, a lead, and a jumper cable each take a few hundred millivolts on the way to the module; a product with PWR-DC12 outlets publishes the voltage it delivers at its rated current.

A product with a DC-VH2, DC-DIN4, DC-MF6, or DC-MF8 DC entry shall implement the pin functions tabulated for that variant (DC-005). The receptacle and plug named are reference parts; an interchangeable part rated for the published current may be used.

DC-VH2 pins

DC-DIN4 pins

DC-MF6 pins

DC-MF8 pins

Modules with a DC entry

A barrel DC entry, and every case DC entry, shall tolerate reverse polarity without damage (DC-006). A computer supply's 8-pin EPS12V cable is a Mini-Fit Jr 2 × 4 like DC-MF8, with its +12 V on the other row: it may mate a DC-MF8 entry reversed.

A module may have both a power header and a DC entry. The rules of 6.1 and 6.3 cover it: it does not require both entries connected at once (PWR-003), and the installer connects one (ASM-003); it does not feed its DC rail onto the bus (PWR-004); and its DC rail's −V is its 0 V (GND-001). While the DC entry carries the load, its published bus currents (PWR-001) state what it draws from the bus, which may be nothing.

Cables

A straight DC barrel cable shall connect tip to tip and sleeve to sleeve at both ends (DC-007). A cable for a DC-VH2, DC-DIN4, DC-MF6, or DC-MF8 DC entry shall connect each pin to the same pin and function at both ends (DC-008).

Distribution to modules

A product with PWR-DC12 outlets to modules, a bus board, a DC entry panel, or a power supply (SUP-009), shall feed them only through DC-BAR21 jacks or DC-VH2 headers, never DC-BAR25 (DC-009). A product with PWR-DC12 outlets to modules shall protect each output separately and shall publish the current at which the protection acts (DC-012), so that one shorted cable takes down one module and not the rail. Its own DC entry shall tolerate reverse polarity without damage and shall not pass the reversed voltage to its outlets (DC-013). Its outputs to a supply or a bus board are row wiring on M4 terminals (6.1), not outlets to modules.

A cable from a PWR-DC12 outlet to a module shall end in DC-BAR21 plugs or DC-VH2 housings and connect +V to +V and −V to −V, tip and pin 1 being +V (DC-010).

8.2 Video on 75 Ω coaxial jacks (VID-75)

VID-75 is the 75 Ω coaxial interface of EIS: video between products on 75 Ω coaxial cable with RCA, BNC, or SMA jacks. It carries a row's video sync, black burst or bi-level or tri-level video sync of an 8.3 format, behind the panel from one source to every module that locks to it. A video sync distributor is a product, usually a bus board, with buffered COAX-THRU ports beside its COAX-IN, which fans the video sync out to several modules. The tables are in data/video_75.json.

A picture on a coaxial jack on the front, composite or component video, is not a video sync port: it is listed by its Annex C class (7.3) and follows no rule of this clause.

Video sync ports

A product that generates or locks to an external video sync takes or gives it at a video sync port on its rear (SIG-018), never at a patch jack (SIG-015, 7.1).

Every video sync port shall be a COAX-IN (75 Ω ±5 % to 0 V at the jack), a COAX-OUT (a 75 Ω ±5 % series source driven at twice the line level), or a COAX-THRU, buffered or looped, never a patch jack (V75-010). The tolerance is of the impedance at the jack. EIS recommends a ±1 % resistor for each, which leaves the rest of the tolerance to the buffer and the jack. Line level is defined below.

The difference a buyer needs most: a COAX-OUT can be the row's video sync, a COAX-IN follows it, and a COAX-THRU is neither a source nor a second input. The rules of each mode apply to a product that has a port of that mode:

• COAX-IN, video sync input. A product with a video sync input shall take the video sync at a COAX-IN on its rear, lock any video timing of its own to it, and list the formats it accepts (V75-006): the ones it locks to, or, on a distributor, the ones it passes.
• COAX-OUT, video sync output. A product with a video sync output shall generate video sync of a listed format itself and give it at a COAX-OUT on its rear (V75-007). A copy of the video sync it takes at its COAX-IN is a COAX-THRU, not a COAX-OUT.
• COAX-THRU, video sync through. A product shall have a video sync through only if it also has a video sync input (V75-008). Each through shall be a COAX-THRU, marked THRU, and its port list shall say which kind, buffered or looped (V75-008).

The two kinds of COAX-THRU:

• Buffered: a copy of the video sync at the COAX-IN, driven as a COAX-OUT into one COAX-IN load. Each THRU drives the next module's input, and a chain of about 18 keeps a tri-level edge inside its tolerance (Topology, V75-012).
• Looped: a jack bridged to the COAX-IN jack on one line. One cable run passes every module and only the last one terminates it, so the run takes no power and no buffer, but every module on it bridges the line. A product with a looped COAX-THRU shall give its COAX-IN a termination switch, marked TERM, that presents 75 Ω to 0 V across the line when on and no load when off, and shall lock the same with the switch on or off (V75-009). EIS recommends that a looped THRU with TERM off bridge the line at 10 kΩ or more in parallel with 20 pF or less.

Video sync ports are an optional interface (Part 3): a module, a bus board, or an enclosure may have them. The claim file lists each port with its mode and formats, and each COAX-IN, COAX-OUT, or COAX-THRU in that list brings in the rules of its mode. Distribution is a capability of whatever product has a COAX-IN and buffered COAX-THRU ports, not a product type: a distributing bus board claims EIS draft, bus board (6.5) (6.5).

Signal and line level

The video sync waveform follows the selected 8.3 format:

• black burst for the two interlaced formats;
• bi-level video sync for any standard-definition format;
• tri-level video sync for any high-definition format.

Line level, in this clause, is the level of the signal's own standard at a terminated input:

• black burst: the 1 V p-p composite scale, pulse tip −300 mV and white +700 mV (−286 mV and +714 mV for 525i59.94, per SMPTE ST 170);
• bi-level video sync alone: 300 mV p-p, pulse tip −300 mV (−286 mV for 525i59.94), blanking 0 V;
• tri-level video sync: ±300 mV about blanking (SMPTE ST 274 and ST 296).

A buffered distributor may AC-couple its buffered THRU outputs when its manual says so.

Jacks

Every jack in a VID-75 tree shall be an RCA, BNC, or SMA jack (V75-001). On every jack in a VID-75 tree, the center pin shall carry the video signal and the shell shall be 0 V (V75-002). A video sync port shall be marked beside it as an input (IN), an output (OUT), or a through (THRU), and a termination switch shall be marked TERM (V75-011). EIS recommends that each jack be insulated from the panel (7.1).

No jack inside the case is a BNC (SIG-017, 7.1). A video sync port on the rear of a module or on a bus board is therefore an RCA or an SMA, and a facility video sync arrives at a BNC on the enclosure's wall, wired inside to RCA or SMA.

The three jack types are electrically the same here. An SMA jack is a 50 Ω connector, a catalog BNC jack is as often 50 Ω as 75 Ω, and an RCA jack has no controlled impedance; but each is electrically short below 100 MHz, so the discontinuity does not matter and either BNC impedance serves. A product picks the type that suits its panel, and a cable may change type from one end to the other. A cable's SMA end is a 50 Ω assembly, and the same argument covers it.

Topology

A tree is the star of cables from one source to the COAX-IN of every module in it. The source is a COAX-OUT, or an external video sync at one COAX-IN; the branches are buffered COAX-THRU ports, or one looped run. Each COAX-IN on the tree is named in its module's port list (V75-006) and terminated as every COAX-IN is (V75-010).

• A COAX-OUT or a buffered COAX-THRU shall drive one COAX-IN load, and an output shall not be split passively to several terminated ports (V75-003). A second termination on the same output drops the level to two thirds, and a third to half.
• A COAX-OUT port or a buffered COAX-THRU port shall pass the video sync with a −3 dB bandwidth of at least 30 MHz into a 75 Ω load (V75-012). A tri-level video sync edge is 54 ns ± 20 ns (SMPTE ST 274 and ST 296), and a 30 MHz stage adds about 12 ns of rise in quadrature, so a 54 ns edge stays inside that tolerance through about 18 buffered THRUs.
• A looped run is one line: it is terminated once, at the module whose TERM is on, and every other module on it bridges it.

Cables

A VID-75 cable shall be a 75 Ω coaxial cable, with RCA, BNC, or SMA plugs, that connects center pin to center pin and shell to shell at both ends (V75-004).

Summary

8.3 Video timing

EIS defines the video timing formats tabulated below: four standard-definition (SD) and fourteen high-definition (HD) rasters. The three 1080-line formats at 50, 59.94, and 60 frames per second are listed because display equipment defaults to them; on an analog component interface at 148.5 MHz they are rare, and a port lists one only when it generates or locks to it.

A product's port list shall name, for each video sync input (COAX-IN) and output (COAX-OUT), every format of clause 8.3 the port accepts or generates, by its format ID (VID-001). A port may list one format or all of them. A COAX-THRU carries the formats of its COAX-IN, and a patch jack lists none (7.1). A format that is not in the table is listed under its own name, and EIS says nothing about it.

For each format a port lists, the video timing a product generates at a COAX-OUT, and the video timing it locks to at a COAX-IN, shall match the format's publication within the tolerances that publication states (VID-002). For a progressive format, and along the line for a high-definition interlaced format, the row below is that publication's raster, sample for sample. For the two standard-definition interlaced formats the row is the reference raster: the publication's figures in microseconds, with the digital active line placed as ITU-R BT.601 places it against the timing reference OH, 16 and 122 luminance samples for the 525-line system and 12 and 132 for the 625-line system.

Composite color encoding (NTSC or PAL) applies only to the interlaced SD formats. A component output (YPbPr, RGBS, RGSB, or RGBHV) may use any listed format. A port that locks to an external video sync takes the selected format; EIS does not require format conversion.

Formats

The tables are generated from data/video_timings.json, where each row cites its publication: SMPTE or ITU, and CTA-861 for the two progressive SD formats.

Progressive SD. 480p59.94 and 576p50 are the 720 × 480 and 720 × 576 progressive rasters CTA-861 tabulates (video format timings 2 and 3, and 17 and 18), the rasters display equipment accepts. SMPTE ST 293, with 483 active lines, and ITU-R BT.1358 are the production systems they descend from, not what the rows reproduce.

Sample clocks are exact:

• SD formats at 27.000 MHz: two samples per 13.5 MHz luma sample for the interlaced formats, so 525i59.94 has 1716 samples per line; one per luma sample for the progressive formats, so 480p59.94 has 858.
• HD formats at 74.25 MHz or 74.25/1.001 MHz.
• The three 1080p formats at 50 Hz and above at 148.5 MHz or 148.5/1.001 MHz.

Horizontal columns. H front runs from the end of active picture to the timing reference OH; H back runs from the end of horizontal video sync to the start of active picture.

• SD: OH is the leading edge of the bi-level video sync pulse, and H video sync is that pulse.
• HD: OH is the zero crossing of the tri-level pulse. The negative half of the pair lies at the end of the front porch and is counted there; H video sync is the positive half, from OH to its trailing edge.

For example, a 1080-line row at 60, 59.94, 30, or 29.97 Hz reads 88 | 44 | 148: ST 274's 44 samples from the end of active picture to the pair, 44 negative, 44 positive, and 148 of back porch. A 720p60 or 720p59.94 row reads 110 | 40 | 220, ST 296's 70, 40, 40, and 220. At the other rates only H front widens, to fill the longer line.

Vertical columns. V front and V video sync count whole lines per frame, the two fields of an interlaced format added together. For the interlaced SD formats, the front porch is the pre-equalizing lines and the video sync the broad-pulse lines of each field. A whole-line count cannot express a half line: ST 274 starts field 2's video sync of 1080i at mid-line, so its front porch is 2.5 lines after field 1's picture and 2 after field 2's, 4.5 per frame, where the row's count is 4. Active lines are the count each publication gives for the format.

Rates. A fractional rate is exact: 59.94, 29.97, and 23.98 are the familiar names of 60/1.001, 30/1.001, and 24/1.001 Hz, the rates a 1.001 sample clock gives. The Rate column prints the exact form, vertical_rate in the data file; vertical_rate_hz beside it carries the rounded name.

Interlaced formats in the publication's terms. The analog publications state a line in microseconds, with tolerances EIS does not restate:

• 525i59.94 (SMPTE ST 170): a 63.556 µs line, a 4.7 µs video sync pulse, a 1.5 µs front porch, and about 10.9 µs of blanking;
• 625i50 (ITU-R BT.470): a 64 µs line, a 4.7 µs video sync pulse, a 1.5 µs front porch, and 12 µs of blanking.

A port meets VID-002 inside those tolerances; the row is where a sample-domain design places the active line.

Line. Samples at the sample clock: total per line, active picture, front porch, video sync, back porch.

Frame. Lines per frame: total, active, front porch, video sync; the rate is the field rate of an interlaced format and the frame rate of a progressive one. SD marks the four standard-definition formats.

Picture bandwidth

A format's picture bandwidth is the luma bandwidth its publication specifies for an analog interface. For the two CTA-861 formats, whose publication is digital only, it is half the luma sample rate. The bandwidth of a VIDEO path is compared with it (7.3); the figure is a property of the format, and EIS requires no path to reach it.

Phase

A module that locks to video sync produces its output a fixed time after the video sync. EIS recommends publishing that offset, horizontal and in nanoseconds, at each listed format, and any adjustment the module offers, so that several generators locked to one video sync can be lined up on the screen.

Verification

A maker compares samples per line, lines per frame, field or frame rate, and video sync pulse width and placement with the tables and the cited publication. tests/video_timings_contract.py checks every row that has an entry in its test fixture, a timing contract measured on hardware, clock for clock; the three 148.5 MHz rows, 1080p50, 1080p59.94, and 1080p60, are listed from their publication and are not in the contract.