videomancer beta program

Before you test

• Flash 1.0.0-rc.55 UF2 (MCU; embeds same as rc.54)

Testing goals

• Second program change during Casting loads the new bitstream

  high

  1. Routing = Analog In; lock any analog source (NTSC YPbPr is enough). 2. Load Howler, then immediately load Colorbars (or two encoder knobs). 3. After Casting ends, confirm the running program is the second name.

  Pass: FPGA / LCD show the second program. Setting name and bitstream match.

• Analog In program change - 720p60 RGB 1V / YPbPr to HDMI (Aaron)

  high

  1. Routing = Analog In; Analog In = RGB 1V then YPbPr; lock 720p60. 2. HDMI to TV or switcher. Change embedded programs without power cycle.

  Pass: HDMI recovers after every program change; no reboot.

• rc.54 CVBS HDMI pack and HD / Dual / DVI regression

  high

  1. Analog In NTSC/PAL Composite; load Howler and Kintsugi; HDMI usable. 2. HDMI In 720p60 program change. 3. Dual 720p60 loopback; DVI monitor if available.

  Pass: No regression vs rc.54 on those paths.

Previous RC testing instructions

• RC 1.0.0-rc.54, Rebuild remaining embedded YUV444 programs with the rc.53 SD HDMI pack
• RC 1.0.0-rc.53, SD YUV HDMI pack (CVBS to HDMI) + Analog In 720p60 program-change decoder refresh and Analog In HD chroma invert
• RC 1.0.0-rc.52, ADV7181C program-reload reset + multi-modulator FPGA sync; MCU-only vs rc.48
• RC 1.0.0-rc.50, PAL/CVBS program-change lifecycle fix — encoder reset hold, deferred SD CVBS configure until VSYNC, sync retry; MCU-only vs rc.48
• RC 1.0.0-rc.49, PAL/CVBS program-change fix for Dual/Analog RGB 1V; ADV7393 reset hold; MCU-only vs rc.48 (embedded programs unchanged)
• RC 1.0.0-rc.48, SDK sync-path HD timing closure; all 27 embedded programs rebuilt; program library 1.0.6 (bleach + vertigo) on SD
• RC 1.0.0-rc.47, SD/ED YUV HDMI primary-accurate Colorbars via limited-range HDMI pack + ADV7513 Table 59 CSC; HD YUV BT.601 AVI; rebuild YUV standalone bitstreams
• RC 1.0.0-rc.46, SD/ED YUV HDMI true RGB via ADV7513 CSC; confirm colorbars on RGB sinks and no HD/Dual regressions vs rc.45
• RC 1.0.0-rc.45, rc.44 dual analog firmware with desk HIL gate at 180/184; confirm anchor legs and heavy HD Dual programs on your bench
• RC 1.0.0-rc.44, Dual analog loopback fixes (RGsB, composite/S-Video, YPbPr AC EXT sync at HD) and Gate E 27/27 program scan; flash rc.44 and verify anchor legs on dual loops
• RC 1.0.0-rc.43, H Phase Out/In dual IO trim, unified Sync Out LC fix, and full 27-program HD Dual rebuild; flash rc.43 UF2 and verify h-phase + heavy programs on dual loops
• RC 1.0.0-rc.42, HD progressive dual passthru fix (ADV7181 CP + RTL sync delay); flash rc.42 UF2 and verify 720p/1080p dual analog loops plus PAL 576i regression
• RC 1.0.0-rc.41, PAL dual 576i passthru fix (ADV7181 CP + RTL sync delay); flash rc.41 UF2 and verify PAL/NTSC dual analog loops and program pack install
• RC 1.0.0-rc.40, Program-library upload reliability (watchdog during SD writes); verify Connect pack install and no dual RGB 1V / HDMI regression vs rc.39
• RC 1.0.0-rc.39, Dual-mode RGB 1V accuracy — EXT sync delay + encoder CSC; verify dual loopback bars at 720p60/1080p30 and no YPbPr AC / HDMI regression
• RC 1.0.0-rc.38, MCU-only ADV7181C SD YPbPr lock fix — clamp/STDI/PLL thrash; verify DVD component reads NTSC (not 480p) with stable lock
• RC 1.0.0-rc.37, Sync timing hardening — Sync Out v_eff_lines wrap (Fix C), FPGA-load vsync watchdog gate, HDMI sync/pixel co-timing; verify 1080i Sync Out and no blank/drop on program switch
• RC 1.0.0-rc.36, Analog I/O mode expansion — YYY out (triple luma + sync on all), RGsB label, YPbPr 1V and YYY 1V analog in on the DC jacks
• RC 1.0.0-rc.35, Sync Out eq/VBI phase advance fix — uniform horizontal sync compensation on tri-level eq/VBI paths; verify 1080i5994 external ramp strobing resolved
• RC 1.0.0-rc.34, Processing-delay chroma inversion fix — Sync Out phase advance uses truthful program_top I/O latency (÷4); verify chroma phase on former odd-delay programs
• RC 1.0.0-rc.33, Unified sync phase compensation — external sync output pre-compensates for program pipeline delay across Analog, HDMI, Dual, and Standalone routing
• RC 1.0.0-rc.32, Dual Mode sync output alignment — dedicated sync output tracks ADV7393 analog video timing when HDMI provides sync to the decoder path
• RC 1.0.0-rc.31, Audio/CV input stability — per-line CV sampling fixes, ADC DMA recovery, and extended-soak validation for rear input monitor + modulators
• RC 1.0.0-rc.30, Standalone RGB 1V input sampling — ADV7181C remains master pixel clock while rear analog RGB is passed through the pipeline; 480p/576p standalone vid_clk fix
• RC 1.0.0-rc.29, rc.25→rc.29 cumulative field test — video sync & boot routing, USB host stability, settings persistence, program library, AudioIn modulator, Pendulum fix, and new MOTION diagnostic pages
• RC 1.0.0-rc.28, USB host stability, program library install, HDMI cold boot

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