videomancer beta program

Before you test

• Flash 1.0.0 stable UF2 (Connect or Downloads)
• Confirm 1.0.0 on the SYSTEM screen
• LZX Connect 1.3.5+
• Dual cable set for YPbPr and RGB 1V loops

Testing goals

• Stable 1.0.0 flash and version

  high

  1. Flash 1.0.0 via Connect or BOOTSEL .uf2. 2. SYSTEM screen shows 1.0.0 (not rc.x).

  Pass: Version correct; boot clean; program library loads.

• H Phase Out/In — dual IO (regression)

  high

  1. Routing = Dual; YPbPr and RGB 1V at 720p60 / 1080p30. 2. Adjust H Phase Out and H Phase In; confirm smooth horizontal trim.

  Pass: Locked picture; no bar crush or chroma swap vs rc.43 beta.

• Heavy programs on HD Dual

  high

  1. Load Lumarian, Moire, Mycelium, Pinwheel at 1080p30 Dual.

  Pass: Programs load; stable picture on YPbPr loop.

• Connect 1.x update path

  medium

  1. From rc.43 or earlier 1.x, update to 1.0.0 via Connect.

  Pass: Download, flash, and reboot without USB hang.

• Official SD program pack

  medium

  1. Install official pack via Connect after stable flash.

  Pass: Signed pack installs; non-embedded programs load from SD.

Previous RC testing instructions

• RC 1.0.0-rc.70, Program library installs keep the watchdog fed while creating SD folders, so official and community updates no longer reset the device on a slow card.
• RC 1.0.0-rc.69, Rear-jack modulation 1.0.0 contract: nothing patched rests at Manual, 1 V at Gain 100% is full range, Audio In follows loudness, shared Off–5 s time curve
• RC 1.0.0-rc.68, Auto is the default for video route and analog in; HDMI beats analog beats standalone, and SD composite burst selects CVBS under analog Auto
• RC 1.0.0-rc.67, Audio In follows one rear jack on the assigned parameter for the whole frame, and channel 1 is the center and default jack
• RC 1.0.0-rc.66, Program selection stays available after the FPGA unloads with no video lock
• RC 1.0.0-rc.65, The LCD keeps following knobs after a restart when no video signal is locked and the FPGA unloads
• RC 1.0.0-rc.64, Front panel keeps scanning after boot when the sync pin edges during FPGA configuration
• RC 1.0.0-rc.63, Video-path consolidation, SD Sync Out seeding, PAL SFL, and program libraries 1.0.8-rc.1 (official) and 1.0.6-rc.1 (community)
• RC 1.0.0-rc.62, Analog In sync-loss recovery without reboot; Colorbars RGB on CVBS; YPbPr ESG3 desk HIL
• RC 1.0.0-rc.61, Analog In RGB 1V + external sync → RGB out recovers after program change without power cycle
• RC 1.0.0-rc.60, Analog In PAL HDMI lock (576i) with centered picture; NTSC HDMI and PAL CVBS must not regress
• RC 1.0.0-rc.59, Analog In program change without cable reseat (ADV7181C STDI/SOG recovery)
• RC 1.0.0-rc.58, Analog In NTSC HDMI 480i color + interlace + left-edge fix (Style-3 YCbCr passthrough)
• RC 1.0.0-rc.57, rc.56 NTSC CVBS/SFL + SD HDMI 480i fixes; Bitcullis FPGA RAM fit (27/27 embeds)
• RC 1.0.0-rc.56, NTSC CVBS chroma + SFL GenLock fix; SD NTSC HDMI 480i AVID/DE alignment
• RC 1.0.0-rc.55, MCU fix: program change during Casting actually loads; post-CRESET ADV7181C reset on Analog In
• RC 1.0.0-rc.54, Rebuild remaining embedded YUV444 programs with the rc.53 SD HDMI pack
• RC 1.0.0-rc.53, SD YUV HDMI pack (CVBS to HDMI) + Analog In 720p60 program-change decoder refresh and Analog In HD chroma invert
• RC 1.0.0-rc.52, ADV7181C program-reload reset + multi-modulator FPGA sync; MCU-only vs rc.48
• RC 1.0.0-rc.50, PAL/CVBS program-change lifecycle fix — encoder reset hold, deferred SD CVBS configure until VSYNC, sync retry; MCU-only vs rc.48
• RC 1.0.0-rc.49, PAL/CVBS program-change fix for Dual/Analog RGB 1V; ADV7393 reset hold; MCU-only vs rc.48 (embedded programs unchanged)
• RC 1.0.0-rc.48, SDK sync-path HD timing closure; all 27 embedded programs rebuilt; program library 1.0.6 (bleach + vertigo) on SD
• RC 1.0.0-rc.47, SD/ED YUV HDMI primary-accurate Colorbars via limited-range HDMI pack + ADV7513 Table 59 CSC; HD YUV BT.601 AVI; rebuild YUV standalone bitstreams
• RC 1.0.0-rc.46, SD/ED YUV HDMI true RGB via ADV7513 CSC; confirm colorbars on RGB sinks and no HD/Dual regressions vs rc.45
• RC 1.0.0-rc.45, rc.44 dual analog firmware with desk HIL gate at 180/184; confirm anchor legs and heavy HD Dual programs on your bench
• RC 1.0.0-rc.44, Dual analog loopback fixes (RGsB, composite/S-Video, YPbPr AC EXT sync at HD) and Gate E 27/27 program scan; flash rc.44 and verify anchor legs on dual loops
• RC 1.0.0-rc.43, H Phase Out/In dual IO trim, unified Sync Out LC fix, and full 27-program HD Dual rebuild; flash rc.43 UF2 and verify h-phase + heavy programs on dual loops
• RC 1.0.0-rc.42, HD progressive dual passthru fix (ADV7181 CP + RTL sync delay); flash rc.42 UF2 and verify 720p/1080p dual analog loops plus PAL 576i regression
• RC 1.0.0-rc.41, PAL dual 576i passthru fix (ADV7181 CP + RTL sync delay); flash rc.41 UF2 and verify PAL/NTSC dual analog loops and program pack install
• RC 1.0.0-rc.40, Program-library upload reliability (watchdog during SD writes); verify Connect pack install and no dual RGB 1V / HDMI regression vs rc.39
• RC 1.0.0-rc.39, Dual-mode RGB 1V accuracy — EXT sync delay + encoder CSC; verify dual loopback bars at 720p60/1080p30 and no YPbPr AC / HDMI regression
• RC 1.0.0-rc.38, MCU-only ADV7181C SD YPbPr lock fix — clamp/STDI/PLL thrash; verify DVD component reads NTSC (not 480p) with stable lock
• RC 1.0.0-rc.37, Sync timing hardening — Sync Out v_eff_lines wrap (Fix C), FPGA-load vsync watchdog gate, HDMI sync/pixel co-timing; verify 1080i Sync Out and no blank/drop on program switch
• RC 1.0.0-rc.36, Analog I/O mode expansion — YYY out (triple luma + sync on all), RGsB label, YPbPr 1V and YYY 1V analog in on the DC jacks
• RC 1.0.0-rc.35, Sync Out eq/VBI phase advance fix — uniform horizontal sync compensation on tri-level eq/VBI paths; verify 1080i5994 external ramp strobing resolved
• RC 1.0.0-rc.34, Processing-delay chroma inversion fix — Sync Out phase advance uses truthful program_top I/O latency (÷4); verify chroma phase on former odd-delay programs
• RC 1.0.0-rc.33, Unified sync phase compensation — external sync output pre-compensates for program pipeline delay across Analog, HDMI, Dual, and Standalone routing
• RC 1.0.0-rc.32, Dual Mode sync output alignment — dedicated sync output tracks ADV7393 analog video timing when HDMI provides sync to the decoder path
• RC 1.0.0-rc.31, Audio/CV input stability — per-line CV sampling fixes, ADC DMA recovery, and extended-soak validation for rear input monitor + modulators
• RC 1.0.0-rc.30, Standalone RGB 1V input sampling — ADV7181C remains master pixel clock while rear analog RGB is passed through the pipeline; 480p/576p standalone vid_clk fix
• RC 1.0.0-rc.29, rc.25→rc.29 cumulative field test — video sync & boot routing, USB host stability, settings persistence, program library, AudioIn modulator, Pendulum fix, and new MOTION diagnostic pages
• RC 1.0.0-rc.28, USB host stability, program library install, HDMI cold boot

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