videomancer beta program
The preset screen now closes on the next knob or switch movement, and official program library 1.0.11 fixes Pong and Shadebob on interlaced video (NTSC, PAL, 1080i). Everything from rc.5 is carried over. This candidate has not been through the desk bench.
Active RC: 1.0.2-rc.6Before you test
- Flash 1.0.2-rc.6 UF2 (full image) via LZX Connect with Show pre-releases on
- Install official program library 1.0.11 with LZX Connect
- LZX Connect 1.3.10 or newer (1.3.14 recommended)
Testing goals
The preset screen closes on the next knob or switch
high1. Press STATE and load a program preset. 2. Turn any knob, then repeat and flip a switch instead.
Pass: Each time, the display leaves the preset screen and shows the modulator page for that control.
Shadebob fills the screen on interlaced video
high1. Set the video standard to NTSC (or PAL, or 1080i) and load Shadebob. 2. Let the bobs run for a minute; compare with 480p or 1080p.
Pass: The bobs and trails reach the bottom of the picture, as on progressive formats.
Pong keeps its shape on interlaced video
high1. Set the video standard to NTSC (or PAL, or 1080i) and load Pong. 2. Play a rally; sweep Pad Size and P1 Pos; turn Wide on and off.
Pass: The court, net, score, ball and paddles have the same proportions as on 480p or 1080p; the ball bounces off the top and bottom walls and the paddle edges are clean.
Bitcullis still in colour
medium1. Load Bitcullis on a colour source and sweep the decimation controls.
Pass: The picture keeps the source's colours.
Known issues
Previous RC testing instructions
- RC 1.0.2-rc.5, The built-in Bitcullis program is in colour again; it had shown only brightness since 1.0.0. Everything from rc.4 (bipolar Gain/Depth attenuverters) is carried over. This candidate has not been through the desk bench.
- RC 1.0.2-rc.4, Every modulation Gain and Depth knob is now a bipolar attenuverter: center is null, right is positive, left inverts, with the same full-scale gain at either end. Presets saved on earlier firmware should load sounding the same. The sideload recovery from rc.3 is carried over. This candidate has not been through the desk bench.
- RC 1.0.2-rc.3, Programs sideloaded with Upload Program in LZX Connect should load even when the FPGA misses its first configuration, and the failure should say what went wrong instead of "bitstream read failed". Library installs, the picker and MIDI Assign fixes from rc.2 are carried over. This candidate has not been through the desk bench.
- RC 1.0.2-rc.2, Program library installs over LZX Connect should complete, including when started right after power-on, and run several times faster than before. The picker and MIDI Assign fixes from rc.1 are carried over. This candidate has not been through the desk bench, so field timings matter most.
- RC 1.0.2-rc.1, The program picker's author scan no longer stalls the panel: choosing an author shows Scanning n/m and then the program list, and MIDI Assign only opens for a switch that is really held. This candidate has not been through the desk bench yet, so field reports on a full SD library matter most.
- RC 1.0.0, Stable 1.0.0 ship gate — rc.43+ validated on desk, Sync Out scope verified, progressive vmtest regress green, FAQ/manual updated
- RC 1.0.0-rc.70, Program library installs keep the watchdog fed while creating SD folders, so official and community updates no longer reset the device on a slow card.
- RC 1.0.0-rc.69, Rear-jack modulation 1.0.0 contract: nothing patched rests at Manual, 1 V at Gain 100% is full range, Audio In follows loudness, shared Off–5 s time curve
- RC 1.0.0-rc.68, Auto is the default for video route and analog in; HDMI beats analog beats standalone, and SD composite burst selects CVBS under analog Auto
- RC 1.0.0-rc.67, Audio In follows one rear jack on the assigned parameter for the whole frame, and channel 1 is the center and default jack
- RC 1.0.0-rc.66, Program selection stays available after the FPGA unloads with no video lock
- RC 1.0.0-rc.65, The LCD keeps following knobs after a restart when no video signal is locked and the FPGA unloads
- RC 1.0.0-rc.64, Front panel keeps scanning after boot when the sync pin edges during FPGA configuration
- RC 1.0.0-rc.63, Video-path consolidation, SD Sync Out seeding, PAL SFL, and program libraries 1.0.8-rc.1 (official) and 1.0.6-rc.1 (community)
- RC 1.0.0-rc.62, Analog In sync-loss recovery without reboot; Colorbars RGB on CVBS; YPbPr ESG3 desk HIL
- RC 1.0.0-rc.61, Analog In RGB 1V + external sync → RGB out recovers after program change without power cycle
- RC 1.0.0-rc.60, Analog In PAL HDMI lock (576i) with centered picture; NTSC HDMI and PAL CVBS must not regress
- RC 1.0.0-rc.59, Analog In program change without cable reseat (ADV7181C STDI/SOG recovery)
- RC 1.0.0-rc.58, Analog In NTSC HDMI 480i color + interlace + left-edge fix (Style-3 YCbCr passthrough)
- RC 1.0.0-rc.57, rc.56 NTSC CVBS/SFL + SD HDMI 480i fixes; Bitcullis FPGA RAM fit (27/27 embeds)
- RC 1.0.0-rc.56, NTSC CVBS chroma + SFL GenLock fix; SD NTSC HDMI 480i AVID/DE alignment
- RC 1.0.0-rc.55, MCU fix: program change during Casting actually loads; post-CRESET ADV7181C reset on Analog In
- RC 1.0.0-rc.54, Rebuild remaining embedded YUV444 programs with the rc.53 SD HDMI pack
- RC 1.0.0-rc.53, SD YUV HDMI pack (CVBS to HDMI) + Analog In 720p60 program-change decoder refresh and Analog In HD chroma invert
- RC 1.0.0-rc.52, ADV7181C program-reload reset + multi-modulator FPGA sync; MCU-only vs rc.48
- RC 1.0.0-rc.50, PAL/CVBS program-change lifecycle fix — encoder reset hold, deferred SD CVBS configure until VSYNC, sync retry; MCU-only vs rc.48
- RC 1.0.0-rc.49, PAL/CVBS program-change fix for Dual/Analog RGB 1V; ADV7393 reset hold; MCU-only vs rc.48 (embedded programs unchanged)
- RC 1.0.0-rc.48, SDK sync-path HD timing closure; all 27 embedded programs rebuilt; program library 1.0.6 (bleach + vertigo) on SD
- RC 1.0.0-rc.47, SD/ED YUV HDMI primary-accurate Colorbars via limited-range HDMI pack + ADV7513 Table 59 CSC; HD YUV BT.601 AVI; rebuild YUV standalone bitstreams
- RC 1.0.0-rc.46, SD/ED YUV HDMI true RGB via ADV7513 CSC; confirm colorbars on RGB sinks and no HD/Dual regressions vs rc.45
- RC 1.0.0-rc.45, rc.44 dual analog firmware with desk HIL gate at 180/184; confirm anchor legs and heavy HD Dual programs on your bench
- RC 1.0.0-rc.44, Dual analog loopback fixes (RGsB, composite/S-Video, YPbPr AC EXT sync at HD) and Gate E 27/27 program scan; flash rc.44 and verify anchor legs on dual loops
- RC 1.0.0-rc.43, H Phase Out/In dual IO trim, unified Sync Out LC fix, and full 27-program HD Dual rebuild; flash rc.43 UF2 and verify h-phase + heavy programs on dual loops
- RC 1.0.0-rc.42, HD progressive dual passthru fix (ADV7181 CP + RTL sync delay); flash rc.42 UF2 and verify 720p/1080p dual analog loops plus PAL 576i regression
- RC 1.0.0-rc.41, PAL dual 576i passthru fix (ADV7181 CP + RTL sync delay); flash rc.41 UF2 and verify PAL/NTSC dual analog loops and program pack install
- RC 1.0.0-rc.40, Program-library upload reliability (watchdog during SD writes); verify Connect pack install and no dual RGB 1V / HDMI regression vs rc.39
- RC 1.0.0-rc.39, Dual-mode RGB 1V accuracy — EXT sync delay + encoder CSC; verify dual loopback bars at 720p60/1080p30 and no YPbPr AC / HDMI regression
- RC 1.0.0-rc.38, MCU-only ADV7181C SD YPbPr lock fix — clamp/STDI/PLL thrash; verify DVD component reads NTSC (not 480p) with stable lock
- RC 1.0.0-rc.37, Sync timing hardening — Sync Out v_eff_lines wrap (Fix C), FPGA-load vsync watchdog gate, HDMI sync/pixel co-timing; verify 1080i Sync Out and no blank/drop on program switch
- RC 1.0.0-rc.36, Analog I/O mode expansion — YYY out (triple luma + sync on all), RGsB label, YPbPr 1V and YYY 1V analog in on the DC jacks
- RC 1.0.0-rc.35, Sync Out eq/VBI phase advance fix — uniform horizontal sync compensation on tri-level eq/VBI paths; verify 1080i5994 external ramp strobing resolved
- RC 1.0.0-rc.34, Processing-delay chroma inversion fix — Sync Out phase advance uses truthful program_top I/O latency (÷4); verify chroma phase on former odd-delay programs
- RC 1.0.0-rc.33, Unified sync phase compensation — external sync output pre-compensates for program pipeline delay across Analog, HDMI, Dual, and Standalone routing
- RC 1.0.0-rc.32, Dual Mode sync output alignment — dedicated sync output tracks ADV7393 analog video timing when HDMI provides sync to the decoder path
- RC 1.0.0-rc.31, Audio/CV input stability — per-line CV sampling fixes, ADC DMA recovery, and extended-soak validation for rear input monitor + modulators
- RC 1.0.0-rc.30, Standalone RGB 1V input sampling — ADV7181C remains master pixel clock while rear analog RGB is passed through the pipeline; 480p/576p standalone vid_clk fix
- RC 1.0.0-rc.29, rc.25→rc.29 cumulative field test — video sync & boot routing, USB host stability, settings persistence, program library, AudioIn modulator, Pendulum fix, and new MOTION diagnostic pages
- RC 1.0.0-rc.28, USB host stability, program library install, HDMI cold boot