videomancer beta program
MCU-only ADV7181C SD YPbPr lock fix — clamp/STDI/PLL thrash; verify DVD component reads NTSC (not 480p) with stable lock
Active RC: 1.0.0-rc.38Before you test
- Install LZX Connect and enable **Show pre-release firmware**
- Flash **1.0.0-rc.38** (Connect update or .uf2 from Downloads)
- Confirm **1.0.0-rc.38** on the SYSTEM screen
- DVD or other SD YPbPr source; Vid Assist or known-good NTSC reference helpful
Testing goals
YPbPr DVD — timing NTSC, no double-wide frame
high1. Analog In = **YPbPr** (AC jacks); load **passthru**. 2. Feed DVD (or other SD) component out. 3. Confirm SYSTEM / timing UI shows **NTSC** (not 480p). 4. Watch analog and HDMI out — no left-to-right double frame; TV accepts format.
Pass: Timing stays NTSC while locked; picture is single-frame geometry; destination display does not report invalid format for NTSC/480i.
YPbPr — Y unplug/replug lock recovery
high1. From a locked YPbPr NTSC source, unplug and replug **Y** only. 2. Watch for vertical thrash / intermittent blank lasting more than a few fields.
Pass: Relock within a few seconds without sustained vertical jumping or stuck unlock.
Composite control — SDP path unchanged
medium1. Same player on **Composite** (CVBS) into Analog In. 2. Confirm lock and picture remain usable.
Pass: CVBS path still locks and displays; regression vs rc.37 not introduced.
rc.37 Sync Out / program-load smoke
medium1. Spot-check 1080i Sync Out and a few program switches from the rc.37 goals.
Pass: No obvious regression vs rc.37 on Sync Out or program load.
Previous RC testing instructions
- RC 1.0.0-rc.37 — Sync timing hardening — Sync Out v_eff_lines wrap (Fix C), FPGA-load vsync watchdog gate, HDMI sync/pixel co-timing; verify 1080i Sync Out and no blank/drop on program switch
- RC 1.0.0-rc.36 — Analog I/O mode expansion — YYY out (triple luma + sync on all), RGsB label, YPbPr 1V and YYY 1V analog in on the DC jacks
- RC 1.0.0-rc.35 — Sync Out eq/VBI phase advance fix — uniform horizontal sync compensation on tri-level eq/VBI paths; verify 1080i5994 external ramp strobing resolved
- RC 1.0.0-rc.34 — Processing-delay chroma inversion fix — Sync Out phase advance uses truthful program_top I/O latency (÷4); verify chroma phase on former odd-delay programs
- RC 1.0.0-rc.33 — Unified sync phase compensation — external sync output pre-compensates for program pipeline delay across Analog, HDMI, Dual, and Standalone routing
- RC 1.0.0-rc.32 — Dual Mode sync output alignment — dedicated sync output tracks ADV7393 analog video timing when HDMI provides sync to the decoder path
- RC 1.0.0-rc.31 — Audio/CV input stability — per-line CV sampling fixes, ADC DMA recovery, and extended-soak validation for rear input monitor + modulators
- RC 1.0.0-rc.30 — Standalone RGB 1V input sampling — ADV7181C remains master pixel clock while rear analog RGB is passed through the pipeline; 480p/576p standalone vid_clk fix
- RC 1.0.0-rc.29 — rc.25→rc.29 cumulative field test — video sync & boot routing, USB host stability, settings persistence, program library, AudioIn modulator, Pendulum fix, and new MOTION diagnostic pages
- RC 1.0.0-rc.28 — USB host stability, program library install, HDMI cold boot